Many processors have bugs in their microcode for the CPUID instruction, so sometimes the cache information may be incorrect.
core.cpuid
Identify the characteristics of the host CPU, providing information about cache sizes and assembly optimisation hints. This module is provided primarily for assembly language programmers.
References: Some of this information was extremely difficult to track down. Some of the documents below were found only in cached versions stored by search engines! This code relies on information found in:
- "Intel(R) 64 and IA-32 Architectures Software Developers Manual,
Volume 2A: Instruction Set Reference, A-M" (2007).
- "AMD CPUID Specification", Advanced Micro Devices, Rev 2.28 (2008).
- "AMD Processor Recognition Application Note For Processors Prior to AMD
Family 0Fh Processors", Advanced Micro Devices, Rev 3.13 (2005).
- "AMD Geode(TM) GX Processors Data Book",
Advanced Micro Devices, Publication ID 31505E, (2005).
- "AMD K6 Processor Code Optimisation", Advanced Micro Devices, Rev D (2000).
- "Application note 106: Software Customization for the 6x86 Family",
Cyrix Corporation, Rev 1.5 (1998)
- http://www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf
- "Geode(TM) GX1 Processor Series Low Power Integrated X86 Solution",
National Semiconductor, (2002)
- "The VIA Isaiah Architecture", G. Glenn Henry, Centaur Technology, Inc (2008).
- http://www.sandpile.org/ia32/cpuid.htm
- http://www.akkadia.org/drepper/cpumemory.pdf
- "What every programmer should know about memory",
Ulrich Depper, Red Hat, Inc., (2007).
- "CPU Identification by the Windows Kernel", G. Chappell (2009). http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm
- "Intel(R) Processor Identification and the CPUID Instruction, Application
Note 485" (2009).
Bugs
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Types 2
Cache size and behaviour
size_t sizeSize of the cache, in kilobytes, per CPU. For L1 unified (data + code) caches, this size is half the physical size. (we don't halve it for larger sizes, since normally data size is much greater tha...ubyte associativityNumber of ways of associativity, eg: 1 = direct mapped 2 = 2-way set associative 3 = 3-way set associative ubyte.max = fully associativeuint lineSizeNumber of bytes read into the cache when a cache miss occurs.bool probablyIntelbool probablyAMDstring processorNamechar [12] vendorIDchar [48] processorNameBufferuint featuresuint miscfeaturesuint extfeaturesuint amdfeaturesuint amdmiscfeaturesulong xfeaturesuint maxCoresuint maxThreadsFunctions 51
const(CacheInfo)[5] dataCaches()The data caches. If there are fewer than 5 physical caches levels, the remaining levels are set to size_t.max (== entire memory space)string vendor()Returns vendor string, for display purposes only. Do NOT use this to determine features! Note that some CPUs have programmable vendorIDs.void cpuid_initialization()Variables 51
CacheInfo[5] datacachedataCaches instead.const(CacheInfo)[5] _dataCachesstring _vendorstring _processorbool _x87onChipbool _mmxbool _ssebool _sse2bool _sse3bool _ssse3bool _sse41bool _sse42bool _sse4abool _aesbool _hasPclmulqdqbool _hasRdrandbool _avxbool _vaesbool _hasVpclmulqdqbool _fmabool _fp16cbool _avx2bool _hlebool _rtmbool _avx512fbool _hasRdseedbool _hasShabool _amd3dnowbool _amd3dnowExtbool _amdMmxbool _hasFxsrbool _hasCmovbool _hasRdtscbool _hasCmpxchg8bbool _hasCmpxchg16bbool _hasSysEnterSysExitbool _has3dnowPrefetchbool _hasLahfSahfbool _hasPopcntbool _hasLzcntbool _isX86_64bool _isItaniumbool _hyperThreadinguint _threadsPerCPUuint _coresPerCPUbool _preferAthlonbool _preferPentium4bool _preferPentium1uint steppingProcessor type (vendor-dependent). This should be visible ONLY for display purposes.
uint numCacheLevelscacheLevels instead.CpuFeatures cpuFeatures