core.cpuid

Identify the characteristics of the host CPU, providing information about cache sizes and assembly optimisation hints. This module is provided primarily for assembly language programmers.

References: Some of this information was extremely difficult to track down. Some of the documents below were found only in cached versions stored by search engines! This code relies on information found in:

  • "Intel(R) 64 and IA-32 Architectures Software Developers Manual,

    Volume 2A: Instruction Set Reference, A-M" (2007).

  • "AMD CPUID Specification", Advanced Micro Devices, Rev 2.28 (2008).
  • "AMD Processor Recognition Application Note For Processors Prior to AMD

    Family 0Fh Processors", Advanced Micro Devices, Rev 3.13 (2005).

  • "AMD Geode(TM) GX Processors Data Book",

    Advanced Micro Devices, Publication ID 31505E, (2005).

  • "AMD K6 Processor Code Optimisation", Advanced Micro Devices, Rev D (2000).
  • "Application note 106: Software Customization for the 6x86 Family",

    Cyrix Corporation, Rev 1.5 (1998)

  • http://www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf
  • "Geode(TM) GX1 Processor Series Low Power Integrated X86 Solution",

    National Semiconductor, (2002)

  • "The VIA Isaiah Architecture", G. Glenn Henry, Centaur Technology, Inc (2008).
  • http://www.sandpile.org/ia32/cpuid.htm
  • http://www.akkadia.org/drepper/cpumemory.pdf
  • "What every programmer should know about memory",

    Ulrich Depper, Red Hat, Inc., (2007).

  • "CPU Identification by the Windows Kernel", G. Chappell (2009). http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm
  • "Intel(R) Processor Identification and the CPUID Instruction, Application

    Note 485" (2009).

Bugs

Currently only works on x86 and Itanium CPUs.

Many processors have bugs in their microcode for the CPUID instruction, so sometimes the cache information may be incorrect.

Types 2

structCacheInfo

Cache size and behaviour

Fields
size_t sizeSize of the cache, in kilobytes, per CPU. For L1 unified (data + code) caches, this size is half the physical size. (we don't halve it for larger sizes, since normally data size is much greater tha...
ubyte associativityNumber of ways of associativity, eg: 1 = direct mapped 2 = 2-way set associative 3 = 3-way set associative ubyte.max = fully associative
uint lineSizeNumber of bytes read into the cache when a cache miss occurs.
Fields
bool probablyIntel
bool probablyAMD
string processorName
char [12] vendorID
char [48] processorNameBuffer
uint features
uint miscfeatures
uint extfeatures
uint amdfeatures
uint amdmiscfeatures
ulong xfeatures
uint maxCores
uint maxThreads

Functions 51

fnconst(CacheInfo)[5] dataCaches()The data caches. If there are fewer than 5 physical caches levels, the remaining levels are set to size_t.max (== entire memory space)
fnstring vendor()Returns vendor string, for display purposes only. Do NOT use this to determine features! Note that some CPUs have programmable vendorIDs.
fnstring processor()Returns processor string, for display purposes only
fnbool x87onChip()Does it have an x87 FPU on-chip?
fnbool mmx()Is MMX supported?
fnbool sse()Is SSE supported?
fnbool sse2()Is SSE2 supported?
fnbool sse3()Is SSE3 supported?
fnbool ssse3()Is SSSE3 supported?
fnbool sse41()Is SSE4.1 supported?
fnbool sse42()Is SSE4.2 supported?
fnbool sse4a()Is SSE4a supported?
fnbool aes()Is AES supported
fnbool hasPclmulqdq()Is pclmulqdq supported
fnbool hasRdrand()Is rdrand supported
fnbool avx()Is AVX supported
fnbool vaes()Is VEX-Encoded AES supported
fnbool hasVpclmulqdq(){returnIs vpclmulqdq supported
fnbool fma()Is FMA supported
fnbool fp16c()Is FP16C supported
fnbool avx2()Is AVX2 supported
fnbool hle()Is HLE (hardware lock elision) supported
fnbool rtm()Is RTM (restricted transactional memory) supported
fnbool avx512f()Is AVX512F supported
fnbool hasRdseed()Is rdseed supported
fnbool hasSha()Is SHA supported
fnbool amd3dnow()Is AMD 3DNOW supported?
fnbool amd3dnowExt()Is AMD 3DNOW Ext supported?
fnbool amdMmx()Are AMD extensions to MMX supported?
fnbool hasFxsr()Is fxsave/fxrstor supported?
fnbool hasCmov()Is cmov supported?
fnbool hasRdtsc()Is rdtsc supported?
fnbool hasCmpxchg8b()Is cmpxchg8b supported?
fnbool hasCmpxchg16b()Is cmpxchg8b supported?
fnbool hasSysEnterSysExit()Is SYSENTER/SYSEXIT supported?
fnbool has3dnowPrefetch()Is 3DNow prefetch supported?
fnbool hasLahfSahf()Are LAHF and SAHF supported in 64-bit mode?
fnbool hasPopcnt()Is POPCNT supported?
fnbool hasLzcnt()Is LZCNT supported?
fnbool isX86_64()Is this an Intel64 or AMD 64?
fnbool isItanium()Is this an IA64 (Itanium) processor?
fnbool hyperThreading()Is hyperthreading supported?
fnuint threadsPerCPU()Returns number of threads per CPU
fnuint coresPerCPU()Returns number of cores in CPU
fnbool preferAthlon()Optimisation hints for assembly code.
fnbool preferPentium4()Does this CPU perform better on Pentium4 code than PentiumPro..Core2 code?
fnbool preferPentium1()Does this CPU perform better on Pentium I code than Pentium Pro code?
fnuint cacheLevels() @propertyThe number of cache levels in the CPU.
fnCpuFeatures * getCpuFeatures() @nogc nothrow
fnbool hyperThreadingBit() @property

Variables 51

varCacheInfo[5] datacache
Scheduled for deprecation. Please use dataCaches instead.
varconst(CacheInfo)[5] _dataCaches
varstring _vendor
varstring _processor
varbool _x87onChip
varbool _mmx
varbool _sse
varbool _sse2
varbool _sse3
varbool _ssse3
varbool _sse41
varbool _sse42
varbool _sse4a
varbool _aes
varbool _hasPclmulqdq
varbool _hasRdrand
varbool _avx
varbool _vaes
varbool _hasVpclmulqdq
varbool _fma
varbool _fp16c
varbool _avx2
varbool _hle
varbool _rtm
varbool _avx512f
varbool _hasRdseed
varbool _hasSha
varbool _amd3dnow
varbool _amd3dnowExt
varbool _amdMmx
varbool _hasFxsr
varbool _hasCmov
varbool _hasRdtsc
varbool _hasCmpxchg8b
varbool _hasCmpxchg16b
varbool _hasSysEnterSysExit
varbool _has3dnowPrefetch
varbool _hasLahfSahf
varbool _hasPopcnt
varbool _hasLzcnt
varbool _isX86_64
varbool _isItanium
varbool _hyperThreading
varuint _threadsPerCPU
varuint _coresPerCPU
varbool _preferAthlon
varbool _preferPentium4
varbool _preferPentium1
varuint stepping
Warning: This field will be turned into a property in a future release.

Processor type (vendor-dependent). This should be visible ONLY for display purposes.

varuint numCacheLevels
This field has been deprecated. Please use cacheLevels instead.
varCpuFeatures cpuFeatures